The present invention is related to a circuit for initiating a test mode, and is more particularly related to a circuit for use with an integrated circuit wherein a test mode may be initiated without interfering with other functions of the integrated circuit. The present invention is particularly useful with input/output circuits of an integrated circuit chip.
As technology has developed, more elements have been added to integrated circuit chips while their sizes have been reduced. With the addition of elements, the functions that a given chip can do has become more varied and complex. With the addition of more functions to a chip, it has become desirable to add more terminals or pads for inputting or outputting signals dependent on the function that a chip is performing. However, with the reduction of the size of the chip, the physical space for adding new pads to a chip has been greatly reduced. Thus, various circuits have been devised such that a pad may be used for inputting and outputting more than one signal or initiating more than one function of the chip.
U.S. Pat. No. 4,336,495 by Happe and issued June 22, 1982 for "Integrated Circuit Arrangement In MOS-Technology With Field-Effect Transistor," discloses test circuitry in an integrated circuit which may be used during fabrication to locate faults without providing an extra external test connection. The disclosed test circuitry uses an existing terminal of an integrated circuit that is activated by a voltage of opposite polarity to that used during normal operation.
U.S. Pat. No. 4,298,146 by Draheim et al., and issue Aug. 9, 1983 for "Test Circuit For MOS Devices" discloses a test circuit having two inputs, and in which the test circuit is enabled when a test signal of opposite polarity to that of the supply voltage is applied to the one of the inputs, and a test signal of the same polarity as that of the supply voltage but of a substantially higher magnitude is applied to the other input.
U.S. Pat. No. 4,450,402 by Owen, III and issued May 22, 1984 for "Integrated Circuit Testing Apparatus," discloses an integrated testing apparatus which provides bidirectional coupling of a high voltage either from a source internal to the integrated circuit to an external pin, or from the external pin to the internal source responsive to an enabling signal placed on a second external pin. The testing apparatus is substantially transparent to normal integrated circuit operation when the enabling signal is removed from the second external pin.
Moore et al., "Unique On-Chip Test Structures Enhance E-PROM Manufacturability," Electronics, Sept. 22, 1983, pp. 135-138, discusses E-PROMS having test modes accessed by taking a control pin to an extra high voltage level near 10 volts, and includes a cell having a high-voltage-sensing circuit. When activated by an extra high voltage, the cell lets its voltage propagate to the output of the cell, where the propagated voltage can be measured to determine voltage margins.
Prior art testing circuits in which the test mode is enabled by an extra high voltage require power supplies having a much broader voltage range, thus creating more spurious energy in the same amount of time as would be created by power supplies with lesser range requirements. Using high voltage to enable a testing function also requires that potentially damaging voltage be connected directly to external pins of an integrated circuit.